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revisions ltr description date (yr-mo-da) approved a added k package. added 04 device, two suppliers and 05 device, one supplier. added vendor cage 34335 for devices 01l, 013, and 02l. editorial changes throughout. added vendor cage 34335 for devices 01k, 023, and 02k. redrawn. 91 ? 04 ? 19 m. a. frye b added vendor cage 65786 for devices 01, 02, 03, 04, and 05lx, kx, and 3x. added vendor cage 18324 for devices 01, 02, 04, and 05lx. iaw nor 5962-r079-93. 93 ? 01 ? 28 m. a. frye c added 06 device for one supplier. added test t su2 to table i. editorial changes throughout. redrawn. 93 ? 07 ? 30 m. a. frye d added devices 07-14, added cage 1fn41 for devices 13 and 14, added test i ccsb to table i for devices 13 and 14, and updated text to newer boiler plate. 97 ? 03 ? 04 raymond monnin e changes in accordance with nor 5962-r263-97 97 ? 04 ? 23 raymond monnin f changes in accordance with nor 5962-r341-97 97 ? 06 ? 05 raymond monnin g added powerup-reset parameters to table i, and the waveform as figure 5. updated boilerplate. ksr 98 ? 07 ? 10 raymond monnin h changed minimum ios value for devices 01 thru 06 on table i. value was changed from -50 ma to -30 ma. ksr 99 ? 03 ? 19 raymond monnin j updated boiler plate. ksr 02 - 10 - 10 raymond monnin rev sheet rev j j j sheet 15 16 17 rev status rev j j j j j j j j j j j j j j of sheets sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pmic n/a prepared by kenneth rice standard microcircuit drawing checked by charles reusing defense supply center columbus columbus, ohio 43216 http://www.d scc.dla.mil this drawing is available for use by all departments approved by michael a. frye and agencies of the department of defense drawing approval date 89 ? 11 ? 28 microcircuit, memory, digital, cmos, programmable array logic (eepld), monolithic silicon size a cage code 67268 5962-89841 amsc n/a revision level j sheet 1 of 17 dscc form 2233 apr 97 5962-e540-02 distribution statement a . approved for public release; distribution is unlimited.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 2 dscc form 2234 apr 97 1. scope 1.1 scope . this drawing describes device requirements for mi l-std-883 compliant, non-jan cl ass level b microcircuits in accordance with mil-prf-38535, appendix a. 1.2 part or identifying number (pin) . the complete pin is as shown in the following example: 5962-89841 01 k x drawing number device type case outline lead finish (see 1.2.1) (see 1.2.2) ( see 1.2.3) 1.2.1 device type(s) . the device type(s) shall identify the circuit function as follows: device type generic number circuit function access time 01, 07 22v10 22-input, 10-output, eecmos, architecturally 30 generic, programmable and-or array 02, 08 22v10 22-input, 10-output, eecmos, architecturally 20 generic, programmable and-or array 03, 09 22v10 22-input, 10-output, eecmos, architecturally 15 generic, programmable and-or array 04, 10 22v10 22-input, 10-output, eecmos, architecturally 25 generic, programmable and-or array 05, 11 22v10 22-input, 10-output, eecmos, architecturally 15 generic, programmable and-or array (higher tco, lower fclk2) 06, 12 22v10 22-input, 10-output, eecmos, architecturally 10 generic, programmable and-or array 13 22v10l 22-input, 10-output, eecmos, architecturally 25 generic, programmable and-or array 14 22v10l 22-input, 10-output, eecmos, architecturally 20 generic, programmable and-or array 1.2.2 case outline(s) . the case outline(s) shall be as designated in mil-std-1835 and as follows: outline letter descriptive designator terminals package style k gdfp2-f24 or cdfp3-f24 24 flat pack l gdip3-t24 or cdip4-t24 24 dual-in-line 3 cqcc1-n28 28 square chip carrier 1.2.3 lead finish . the lead finish is as specified in mil-prf-38535, appendix a. 1.3 absolute maximum ratings. supply voltage range ------------------------------------------------------- -0.5 v dc to +7.0 v dc input voltage appli ed ------------------------------------------------------ -0.5 v dc to vcc +1.0 v dc 1/ off-state output voltage app lied ----------------------------------------- -0 .5 v dc to vcc +1.0 v dc 1/ storage temperature range (tstg) ------------------------------------ -65 c to +150 c maximum power dissipati on (pd) 2/ ----------------------------------- 1.5 w lead temperature (soldering, 10 seconds) (t sol) ---------------- +260 c thermal resistance, junction-to-case ( jc) ------------------------- see mil-std-1835 junction temperat ure (tj) ------------------------------------------------- +175 c data retent ion----------------------------------------------------------------- 10 years (minimum) endurance -------------------------------------------------------------------- 100 erase/write cycles (minimum) _______________ 1/ minimum voltage is -0.5 v which may undershoot to -2.5 v for pulses of less than 20 ns. 2/ must withstand the added pd due to short circuit test; e.g., ios.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 3 dscc form 2234 apr 97 1.4 recommended operating conditions . supply voltage range (v cc ) ------------------------------------- 4.5 v dc to 5.5 v dc high level input voltage (v ih ) ----------------------------------- 2.0 v dc to v cc +1.0 v dc low level input voltage (v il ) ----------------------------------- v ss -0.5 v dc to +0.8 v dc high level output current (i oh ) --------------------------------- -2.0 ma maximum low level output current (i ol )----------------------------------- 12 ma maximum case operating temperature range (t c ) -------------------- -55 c to +125 c 2. applicable documents 2.1 government specification, standards, and handbooks . the following specification, standards, and handbooks form a part of this drawing to the extent specified herein. unless otherwise specified, the issues of these documents are those listed in the issue of the department of de fense index of specifications and standards (dodiss) and supplement thereto, cited in the solicitation. specification department of defense mil-prf-38535 - integrated circuits, manufacturing, general specification for. standards department of defense mil-std-883 - test method standard microcircuits. mil-std-1835 - interface standard electronic component case outlines. handbooks department of defense mil-hdbk-103 - list of standard microcircuit drawings. mil-hdbk-780 - standard microcircuit drawings. (unless otherwise indicated, copies of the spec ification, standards, and handbooks are available from the standardization document order desk, 700 robbins avenue, building 4d, philadelphia, pa 19111-5094.) 2.2 order of precedence . in the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. requirements 3.1 item requirements . the individual item requirements shall be in accordance with mil-prf-38535, appendix a for non-jan class level b devices and as specified herein. produc t built to this drawing that is produced by a qualified manufacturer listing (qml) certified and qualified manufac turer or a manufacturer who has been granted transitional certification to mil-prf-38535 may be processed as qml product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance wi th mil-prf-38535. this qml flow as documented in the quality management (qm) plan may make modifications to t he requirements herein. these modifications shall not affect form, fit, or function of the devic e. these modifications shall not affect the pin as described herein. a "q" or "qml" certification mark in accordance with mil-prf-38535 is required to identify when the qml flow option is used. 3.2 design, construction, and physical dimensions . the design, construction, and physical dimensions shall be as specified in mil-prf-38535, appendix a and herein. 3.2.1. terminal connections . the terminal connections sha ll be as specified on figure 1.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 4 dscc form 2234 apr 97 3.2.2 truth table . the truth table shall be as specified on figure 2. 3.2.2.1 unprogrammed devices . the truth table for unprogrammed devic es shall be as specified on figure 2. 3.2.2.2 programmed devices . the truth table for programmed devices sha ll be as specified by an attached altered item drawing. 3.2.3 case outlines the case outlines shall be in accordance with 1.2.2 herein. 3.3 electrical perfo rmance characteristics . unless otherwise specified her ein, the electrical performance characteristics are as specified in table i and sha ll apply over the full case operating temperature range. 3.4 electrical test requirements . the electrical test requirements shall be the subgroups specified in table ii. the electrical tests for each subgroup are described in table i. 3.5 marking . marking shall be in accordance with mil-prf- 38535, appendix a. the part shall be marked with the pin listed in 1.2 herein. in addition, the manufacturer' s pin may also be marked as listed in mil-hdbk-103 (see 6.6 herein). for packages where marking of the entire smd pi n number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 certification/compliance mark . a compliance indicator ?c? shall be marked on all non-jan devices built in compliance to mil-prf-38535, appendix a. the compliance i ndicator ?c? shall be replaced with a "q" or "qml" certification mark in accordance with mil-prf- 38535 to identify when the qml flow option is used. 3.6 certificate of compliance . a certificate of compliance shall be requir ed from a manufacturer in order to be listed as an approved source of supply in mil-hdbk-103 (see 6.6 her ein). the certificate of compliance submitted to dscc-va prior to listing as an approved source of supply s hall affirm that the manufacturer's product meets the requirements of mil-prf-38535, appendi x a and the requirements herein. 3.7 certificate of conformance . a certificate of conformance as required in mil-prf-38535, appendix a shall be provided with each lot of microcir cuits delivered to this drawing. 3.8 notification of change . notification of change to dscc-va shall be required in accordance with mil-prf-38535, appendix a. 3.9 verification and review . dscc, dscc's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentati on. offshore documentation shall be made available onshore at the option of the reviewer.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 5 dscc form 2234 apr 97 table i. electrical per formance characteristics . test symbol conditions group a device limits unit -55 c t c +125 c subgroups type v ss = 0 v, 4.5 v v cc 5.5 v unless otherwise specified min max input leakage current 1 / i lx 0.0 v v in v cc 1, 2, 3 01-06, 13,14 10 -150 a 7-12 -10 10 bidirectional pin leakage current 1 / i i/o/q 0.0 v v i/o/q v cc 1, 2, 3 01-06, 13,14 10 -150 a 7-12 -40 40 output low voltage v ol v cc = 4.5 v, i ol = 12 ma, 1, 2, 3 all 0.5 v v in = v ih or v il output high voltage v oh v cc = 4.5 v, i oh = -2 ma, 1, 2, 3 all 2.4 v v in = v ih or v il input low voltage 2 / v il 1, 2, 3 all 0.8 v input high voltage 2 / v ih 1, 2, 3 all 2.0 v operating power supply current i cc v il = 0.5 v, v ih = 3.0 v 1, 2, 3 01-06 150 ma f tog = 15 mhz 07-12 130 13,14 70 power supply i ccsb v in 0 v or v cc 1, 2, 3 ma current standby f tog = 0 mhz 13,14 15 output short circuit current 3 / i os v cc = 5.0 v, v out = 0.5 v 1, 2, 3 01-06 -30 -135 t a = 25 c see 4.3.1d 07-12 -30 -90 ma input capacitance c in v cc = 5.0 v, v i = 2.0 v 4 all 10 pf f = 1.0 mhz, t a = +25 c, see 4.3.1c bidirectioanl pin capacitance c i/o/q v cc = 5.0 v, v i/o/q = 2.0 v 4 all 10 pf f = 1.0 mhz, t a = +25 c, see 4.3.1c functional tests see 4.3.1e 7, 8a,8b all input or feedback to nonregistered output t pd v cc = 4.5 v, see figures 3 and 4 4 / 9, 10, 11 01 30 ns 02 20 03, 05 15 08, 09, 11 3 15 04 25 06 10 12 3 10 07,10, 13 3 25 14 3 20 see footnotes at end of table.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 6 dscc form 2234 apr 97 table i. electrical per formance characteristics - continued. test symbol conditions group a device limits unit -55 c t c +125 c subgroups type v ss = 0 v, 4.5 v v cc 5.5 v unless otherwise specified min max clock to output delay 5 / t co v cc = 4.5 v see figures 3 9, 10, 11 01,04 20 ns and 4 4 / 02 15 07, 10, 14 2 15 03 8 08, 09, 11 2 8 05 12 06 7 12 2 7 13 2 20 input to output enable t ea 9, 10, 11 01,04, 07,10, 13 25 ns 02, 14 20 03, 05, 08,09, 11 15 06, 12 10 input to output disable 6 / t er 9, 10, 11 01,04, 07,10, 13, 25 ns 02, 14 20 03, 05,08, 09,11 15 06 12 12 10 asynchronous register reset 5 / t res 9, 10, 11 01,04, 13 30 ns 02.07, 10,14 25 03.05, 08,09, 11 20 06,12 12 clock frequency without f clk1 9, 10, 11 01 0 25.0 mhz feedback 5 / 7 / 02,14, 0 33.3 1/(t pwh + t pwl ) 07,10 0 35.7 03, 05 0 62.5 08, 09, 11 0 83.3 04, 13 0 33.0 12 0 142.0 06 0 166.0 see footnotes at end of table.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 7 dscc form 2234 apr 97 table i. electrical per formance characteristics - continued. test symbol conditions group a device limits unit -55 c t c +125 c subgroups type v ss = 0 v, 4.5 v v cc 5.5 v unless otherwise specified min max clock frequency with f clk2 v cc = 4.5 v see figures 3 9, 10, 11 01 0.0 22.0 mhz feedback 5 / 7 / and 4 4 / 07,10 0.0 30.3 1/(t co + t su1 ) 02,14 0.0 31.2 03,08, 09,11 0.0 50.0 04, 13 0.0 26.3 05 0.0 42.0 06,12 0.0 76.9 input or feedback setup t su1 9, 10, 11 01 25 ns time before rising clock 02, 14 17 5 / 03,05 12 08, 09, 10 11 04, 07, 18 10, 13 06, 12 6 synchronous preset t su2 9, 10, 11 01 25 ns setup time 02, 14 17 08, 09, 11 10 03, 05 12 04, 07, 10, 13 18 06, 12 7 input or feedback hold time t h 9, 10, 11 all 0 ns after rising clock 5 / clock pulse width, high t pwh 9, 10, 11 01 20 ns 5 / 02, 14 15 03, 05 8 04, 13 15 07, 10 14 08, 09, 11 6 06, 12 7 / 3 see footnotes at end of table.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 8 dscc form 2234 apr 97 table i. electrical per formance characteristics - continued. test symbol conditions group a device limits unit -55 c t c +125 c subgroups type v ss = 0 v, 4.5 v v cc 5.5 v unless otherwise specified min max clock pulse width, low t pwl v cc = 4.5 v see figures 3 9, 10, 11 01 20 ns 5 / and 4 4 / 02, 14 15 03, 05 8 04, 13 15 07, 10 14 08, 09, 11 6 06, 12 7 / 3 asynchronous reset pulse width t pwr 9, 10, 11 01 30 ns 02, 14 20 03, 05, 08, 09, 11 15 04, 07, 10, 13 25 06, 12 10 asynchronous reset to rising clock recovery time t rec 9, 10, 11 01 30 ns 02, 14 20 03, 05 15 08, 09, 11 12 04, 07, 10, 13 25 06, 12 6 clock pulse width t w see figure 5 9, 10, 11 01, 07 20 ns 5 / 7 / 04, 10, 13 15 02, 08, 14 15 03, 05, 09, 11 8 06, 12 3.5 setup time t s 9, 10, 11 01, 07 25 ns 5 / 7 / 04, 10, 13 18 02, 08, 14 17 03, 05, 09, 11 12 06, 12 6 power up reset time t pr 9, 10, 11 all 1.0 s 7 / see footnotes at end of table.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 9 dscc form 2234 apr 97 table i. electrical per formance characteristics - continued. 1 / the maximum leakage current is due to the internal pull-up resistor on all pins. 2 / these are absolute values with respect to device gr ound and all overshoots due to syst em or tester noise are included. 3 / not more than one output at a time should be shorted. short circuit test duration should not exceed 1 second (see 4.3.1d). 4 / ac tests are performed with input rise and fall times (10 per cent to 90 percent) of 3.0 ns , timing reference levels of 1.5 v, input pulse levels of 0 v to 3.0 v and the output load of figure 3. input pulse levels are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 5 / test applies only to registered outputs. 6 / transition is measured at steady-state high level -500 mv or steady-state low level +500 mv on the output from the 1.5 v level on the input. 7 / tested initially and after any design or process changes that affect that param eter, and therefore shall be guaranteed to the limits specified in table i. table ii. electrical test requirements . mil-std-883 test requirements subgroups (in accordance with mil-std-883, method 5005, table i) interim electrical parameters (method 5004) - - - final electrical test parameters (method 5004) 1*, 2,3, 7*, 8a, 8b, 9, 10, 11 group a test requirements (method 5005) 1, 2,3, 4**, 7, 8a, 8b, 9, 10, 11 groups c and d end-point electrical parameters (method 5005) 2, 3, 7, 8a, 8b * pda applies to subgroups 1 and 7 ** see 4.3.1c
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 10 dscc form 2234 apr 97 device types all devices case outlines k and l 3 terminal number terminal symbol 1 i/clk nc 2 i i/clk 3 i i 4 i i 5 i i 6 i i 7 i i 8 i nc 9 i i 10 i i 11 i i 12 gnd i 13 i i 14 i/o/q gnd 15 i/o/q nc 16 i/o/q i 17 i/o/q i/o/q 18 i/o/q i/o/q 19 i/o/q i/o/q 20 i/o/q i/o/q 21 i/o/q i/o/q 22 i/o/q nc 23 i/o/q i/o/q 24 v cc i/o/q 25 --- i/o/q 26 --- i/o/q 27 --- i/o/q 28 --- v cc figure 1. terminal connections .
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 11 dscc form 2234 apr 97 inputs i/clk i i i i i i i i i i i x x x x x x x x x x x x outputs i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q z z z z z z z z z z z z x = don't care state z = high impedance state figure 2. truth table (unprogrammed) .
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 12 dscc form 2234 apr 97 test r 1 c l (minimum) t pd , t co , t res , f clk1 , f clk2 390 ? 50 pf t ea active high = infinity active low = 390 ? 50 pf t er active high = infinity active low = 390 ? 5 pf notes: 1. cl = load capacitance and includes jig and probe capacitance. 2. a different output load circuit may be utilized, but table i electricals shall be guaranteed with figure 3 output load circuit. figure 3. output load circuit .
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 13 dscc form 2234 apr 97 figure 4. switching waveforms .
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 14 dscc form 2234 apr 97 note: the power-up reset feature ensures that all flip-f lops will be reset to low after the device has been powered up. the following conditions are required: a) the v cc rise must be monotonic. b) after reset occurs, all applicable input and feedback se tup times must be met before driving the clock pin high. c) the clock signal must remain stable beginning prio r to the occurrence of the 10% level and continuing until the end of t pr . figure 5. power-up reset waveform .
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 15 dscc form 2234 apr 97 4. quality assurance provisions 4.1 sampling and inspection . sampling and inspection procedures sha ll be in accordance with mil-prf-38535, appendix a. 4.2 screening . screening shall be in accordance with method 5004 of mil-std-883, and shall be conducted on all devices prior to quality conform ance inspection. the following additional criteria shall apply: a. burn-in test, method 1015 of mil-std-883. (1) test condition d. the test circuit shall be ma intained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipati on, as applicable, in accordance with the intent specified in test method 1015 of mil-std-883. (2) ta = +125c, minimum. (3) devices shall be burned-in containing a pattern that assures all inputs and i/o's are dynamically switched. this pattern must have all cells programm ed in a high or low state (not neutralized). (4) the burn-in pattern shall be read before and after bur n-in. devices having any logic array bits not in the proper state shall constitute a device failure and shall be added as failures for pda calculation. b. interim and final electrical parameter s shall be as specified in table ii herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. an endurance/retention test prior to burn-in (may be performed at wafer level), in accordance with method 1033 of mil-std-883, shall be included as part of t he screening procedure with the following conditions: (1) cycling may be at equipment room ambient temperature and shall cycle all bit locations for a minimim of 100 cycles. after cycling, devices containing bits wh ich fail to verify shall be considered device failures. (2) the retention pattern must have a minimu m of 50 percent of the logic array programmed. (3) after cycling, perform a high temperature unbias ed bake for a minimum of 48 hours at +150c. the bake time may be accelerated by using higher temperatur e in accordance with the arrhenius relationship: a f = acceleration factor (unitless quantity) = t 1 /t 2 . t = temperature in kelvin (i.e., c + 273 = k). t 1 = time (hrs) at temperature t 1 . t 2 = time (hrs) at temperature t 2 . k = boltzmanns constant = 8.62 x 10 -5 ev/k using an apparent activation energy (e a ) of 0.6 ev. the maximum bake temperature shall not exceed +250c. (4) after cycling and bake, and prior to burn-in, read the data retention pattern. test using subgroups 1 and 7 (at the manufacturer's option, high temperature equival ent subgroups 2 and 8a or lo w temperature equivalent subgroups 3 and 8b may be used in lieu of subgroups 1 and 7) . devices having any logic array bits not in the proper state after storage shall constitute device failure. (5) at the manufacturer's option, the testing specifi ed in 4.2c(4) may be deleted if the devices are put into burn-in with no reprogramming allo wed between the start of data ret ention bake and the end of burn-in. exercising this option will result in data retention bake failures being caught and included in post burn-in pda calculations.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 16 dscc form 2234 apr 97 4.3 quality conformance inspection . quality conformance inspection shall be in accordance with method 5005 of mil-std-883 including groups a, b, c, and d inspecti ons. the following additional criteria shall apply. 4.3.1 group a inspection. a. tests shall be as specified in table ii herein. b. subgroups 5 and 6 in table i, met hod 5005 of mil-std-883 shall be omitted. c. subgroup 4 (c in and c i/o/q measurements) shall be measured only for t he initial test and after process or design changes which may affect capacitance. sample size is 15 devices with no failures, and all input and output terminals tested. d. i os measurements in subgroup 1 shall be measured only for the initial test and after process or design changes which may affect i os . sample size is 15 devices with no failures, and all output terminals tested. e. subgroups 7 and 8 shall be sufficient to verify the truth table. 4.3.2 group c inspection. group c inspection shall be in accordance with table iii of method 5005 of mil-std-883 and as follows: a. end-point electrical parameters shall be as specified in table ii herein. b. steady-state life test conditions, method 1005 of mil-std-883. (1) test condition d. the test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipati on, as applicable, in accordance with the intent specified in test method 1005 of mil-std-883. (2) ta = +125c, minimum. (3) test duration: 1,000 hours except as permitted by method 1005 of mil-std-883. (4) all devices shall be programmed with a pattern t hat assures all inputs and i/o's are dynamically switched. c. an extended data retention test shall be added. a new sample shall be selected, and the sample size, accept number and frequency of testing shall be the same as that required for group c inspection. extended data retention shall also consist of the following: (1) all devices shall have a minimum of 50 percent of the logic array programmed with a charge on all cells, such that the cell will not be in a neutral state. (2) unbiased bake for 1,000 hours (minimum) at +150c (minimum). the unbiased bake time may be accelerated by using a higher temperature in accordance with the arrhenius relationship: af = acceleration factor (unitless quantity) = t 1 /t 2 . t = temperature in kelvin (i.e., c + 273 = k). t 1 = time (hrs) at temperature t 1 . t 2 = time (hrs) at temperature t 2 . k = boltzmanns constant = 8.62 x 10-5 ev/k using an apparent activation energy (ea) of 0.6 ev. the maximum bake temperature shall not exceed +200c. (3) read the pattern after bake and perform end-point elec trical tests in accordance with table ii herein for group c.
standard microcircuit drawing size a 5962-89841 defense supply center columbus columbus, ohio 43216-5000 revision level j sheet 17 dscc form 2234 apr 97 4.3.3 group d inspection. group d inspection shall be in accordance with table iv of method 5005 of mil-std-883. end-point electrical param eters shall be as specified in table ii herein. 4.4 programming procedures. the pr ogramming procedures shall be as spec ified by the device manufacturer and shall be made available to the user on request. 4.5 erasing procedures. the erasing procedures shall be as specified by the device manufacturer and shall be made available to the user on request. 5. packaging 5.1 packaging requirements. the requirements for pa ckaging shall be in accordance with mil-prf-38535, appendix a. 6. notes 6.1 intended use. microcircuits conforming to this dr awing are intended for use for government microcircuit applications (original equipment), desi gn applications, and logistics purposes. 6.2 replaceability. microcircuits covered by this dr awing will replace the same generic device covered by a contractor-prepared specif ication or drawing. 6.3 configuration control of smd's. all proposed changes to existing smd's will be coordinated with the users of record for the individual documents. this coordinat ion will be accomplished using dd form 1692, engineering change proposal. 6.4 record of users. military and industrial users shall inform defense supply center columbus when a system application requires configuration control and the applicable sm d. dscc will maintain a record of users and this list will be used for coordination and distribution of changes to t he drawings. users of draw ings covering microelectronics devices (fsc 5962) should contac t dscc-va, telephone (614) 692-0544. 6.5 comments. comments on this drawing should be directed to dscc-va, columbus, ohio 43216-5000, or telephone (614) 692-0547. 6.6 approved sources of supply. a pproved sources of supply are listed in mil-hdbk-103. the vendors listed in mil-hdbk-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by dscc-va.
standard microcircuit drawing source approval bulletin date: 02 - 10 - 10 approved sources of supply for smd 5962-89841 are listed below for immediate acquisition information only and shall be added to mil-hdbk-103 and qml-38535 during the next re vision. mil-hdbk-103 and qml-38535 will be revised to include the addition or deletion of sources. the vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by dscc-va. this bulletin is superseded by the next dated revision of mil-hdbk-103 and qml-38535. standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-8984101la 3 / 3 / 3 / 66675 66675 0c7v7 palc22v10d-30dmb palce22v10-30dmb palce22v10h-30e4/bla gal22v10c-30ld/883c gal22v10d-30ld/883c qpc22v10-30/bla 5962-8984101ka 3 / 3 / 3 / 0c7v7 palc22v10d-30kmb palce22v10-30kmb palce22v10h-30e4/bka qpc22v10-30/bka 5962-89841013a 3 / 3 / 3 / 0c7v7 palc22v10d-30lmb palce22v10-30lmb palce22v10h-30e4/b3a qpc22v10-30/b3a 5962-8984102la 65786 65786 3 / 66675 66675 0c7v7 palc22v10d-20dmb palce22v10-20dmb palce22v10h-20e4/bla gal22v10c-20ld/883c gal22v10d-20ld/883c qpc22v10-20/bla 5962-8984102ka 65786 65786 3 / palc22v10d-20kmb palce22v10-20kmb palce22v10h-20e4/bka 5962-89841023a 66675 66675 3 / 3 / 3 / 0c7v7 gal22v10c-20lr/883c gal22v10d-20lr/883c palc22v10d-20lmb palce22v10-20lmb palce22v10h-20e4/b3a qpc22v10-20/b3a 5962-8984103la 66675 66675 65786 65786 1fn41 gal22v10c-15ld/883c gal22v10d-15ld/883c palc22v10d-15dmb palce22v10-15dmb atf22v10b-15gm/883 5962-8984103lc 6s055 dpa22v10-15lc 5962-8984103ka 3 / 3 / 0c7v7 palc22v10d-15kmb palce22v10-15kmb qpc22v10-15/bka see footnote at end of table. the information contained herein is disseminated for convenience only and the government assumes no liability whatsoever for any inaccuracies in the information bulletin. 1 of 4
standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-89841033a 66675 66675 65786 65786 1fn41 gal22v10c-15lr/883c gal22v10d-15lr/883c palc22v10d-15lmb palce22v10-15lmb atf22v10b-15nm/883 5962-8984104la 3 / 3 / 3 / 66675 66675 3 / 0c7v7 palc22v10d-25dmb palce22v10-25dmb atf22v10b-25gm/883 gal22v10c-25ld/883c gal22v10d-25ld/883c palce22v10h-25e4/bla qpc22v10-25/bla 5962-8984104ka 3 / 3 / 3 / 0c7v7 palc22v10d-25kmb palce22v10-25kmb palce22v10h-25e4/bka qpc22v10-25/bka 5962-89841043a 65786 65786 3 / 3 / palc22v10d-25lmb palce22v10-25lmb atf22v10b-25nm/883 palce22v10h-25e4/b3a 5962-8984105la 65786 65786 1fn41 3 / 0c7v7 palc22v10d-15dmb palce22v10-15dmb atf22v10b-15gm/883 palce22v10h-15e4/bla qpc22v10-15/bla 5962-8984105ka 3 / 3 / 3 / 0c7v7 palc22v10d-15kmb palce22v10-15kmb palce22v10h-15e4/bka qpc22v10-15/bka 5962-89841053a 3 / 3 / 1fn41 3 / palc22v10d-15lmb palce22v10-15lmb atf22v10b-15nm/883 palce22v10h-15e4/b3a 5962-8984106la 65786 65786 66675 66675 1fn41 palc22v10d-10dmb palce22v10-10dmb gal22v10c-10ld/883c gal22v10d-10ld/883c atf22v10b-10gm/883 5962-8984106ka 65786 65786 palc22v10d-10kmb palce22v10-10kmb 5962-89841063a 65786 65786 66675 66675 1fn41 palc22v10d-10lmb palce22v10-10lmb gal22v10c-10lr/883c gal22v10d-10lr/883c atf22v10b-10nm/883 see footnote at end of table. 2 of 4
standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-8984107la 3 / 3 / 0c7v7 palc22v10d-30dmb palce22v10-30dmb qpc22v10-30/bla 5962-8984107ka 3 / 3 / 0c7v7 palc22v10d-30kmb palce22v10-30kmb qpc22v10-30/bka 5962-89841073a 3 / 3 / 0c7v7 palc22v10d-30lmb palce22v10-30lmb qpc22v10-30/b3a 5962-8984108la 65786 65786 0c7v7 palc22v10d-20dmb palce22v10-20dmb qpc22v10-20/bla 5962-8984108ka 65786 65786 0c7v7 palc22v10d-20kmb palce22v10-20kmb qpc22v10-20/bka 5962-89841083a 65786 65786 0c7v7 palc22v10d-20lmb palce22v10-20lmb qpc22v10-20/b3a 5962-8984109la 3 / 3 / 0c7v7 palc22v10d-15dmb palce22v10-15dmb qpc22v10-15/bla 5962-8984109ka 3 / 3 / 0c7v7 palc22v10d-15kmb palce22v10-15kmb qpc22v10-15/bka 5962-89841093a 3 / 3 / 0c7v7 palc22v10d-15lmb palce22v10-15lmb qpc22v10-15/b3a 5962-8984110la 65786 65786 0c7v7 palc22v10d-25dmb palce22v10-25dmb qpc22v10-25/bla 5962-8984110ka 65786 65786 0c7v7 palc22v10d-25kmb palce22v10-25kmb qpc22v10-25/bka 5962-89841103a 65786 65786 0c7v7 palc22v10d-25lmb palce22v10-25lmb qpc22v10-25/b3a 5962-8984111la 3 / 3 / 0c7v7 palc22v10d-15dmb palce22v10-15dmb qpc22v10-15/bla 5962-8984111ka 3 / 3 / 0c7v7 palc22v10d-15kmb palce22v10-15kmb qpc22v10-15/bka see footnote at end of table. 3 of 4
standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-89841113a 3 / 3 / 0c7v7 palc22v10d-15lmb palce22v10-15lmb qpc22v10-15/b3a 5962-8984112la 3 / 3 / 0c7v7 palc22v10d-10dmb palce22v10-10dmb qpc22v10-10/bla 5962-8984112ka 3 / 3 / 0c7v7 palc22v10d-10kmb palce22v10-10kmb qpc22v10-10/bka 5962-89841123a 3 / 3 / 0c7v7 palc22v10d-10lmb palce22v10-10lmb qpc22v10-10/b3a 5962-8984113la 3 / atf22v10bql-25gm/883 5962-89841133a 3 / atf22v10bql-25nm/883 5962-8984114la 3 / atf22v10bql-20gm/883 5962-89841143a 3 / atf22v10bql-20nm/883 1 / the lead finish shown for each pin representing a hermetic package is the most readily available from the manufacturer listed for that part. if the desired lead finish is not listed contact the vendor to determine its availability. 2 / caution . do not use this number for item acquisition. items acquired to this number may not satisfy the performance requirements of this drawing. 3 / no longer available from an approved source of supply. vendor cage vendor name number and address 66675 lattice semiconductor corporation 5555 ne moore court hillsboro, or 97124-6421 65786 cypress semiconductor corporation 3901 north first street san jose, ca 95134 1fn41 atmel corporation 2325 orchard parkway san jose, ca 95131 6s055 dpa laboratories 2251 ward ave. simi valley, ca 93065 0c7v7 qp laboratories 3605 kifer road santa clara, ca 95051 the information contained herein is disseminated for convenience only and the government assumes no liability whatsoever for any inaccuracies in the information bulletin. 4 of 4

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